The photovoltaic solar cell industry is highly cost sensitive in terms of the efficiency of the voltage produced by a solar cell and the cost of producing the solar cell. As only a low percentage of the total thickness of a solar cell is used to generate voltage, it is increasingly important to minimise the thickness of the solar cell and yield more solar cells from a piece of silicon.
International (PCT) Publication No. WO 02/45143 (PCT/AU01/01546) published on 6 Jun. 2002 and entitled “Semiconductor Wafer Processing to Increase the Usable Planar Surface Area” describes “sliver” solar cells and a method of making such sliver solar cells to increase the usable surface area of a semiconductor wafer. The wafer has a substantially planar surface and a thickness dimension at a right angle to the substantially planar surface and is typically single crystal silicon or multicrystalline silicon.
In the method of International Publication No. WO 02/45143, a strip or sliver thickness is selected for division of the wafer into several strips or slivers. A technique is then selected for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer. The wafer is cut into strips using the selected technique, and the strips are separated from each other. The faces of the strips that were previously at an angle to the surface of the wafer become the faces of the strips exposed as a result of cutting the wafer and separating the strips from each other.
FIG. 1(a) illustrates a silicon wafer 3 formed by standard crystal growth and wafering techniques. The wafer 3 may be at least 0.5 mm thick and typically about 1 mm thick and can be single-crystal or a multi-crystalline wafer. In the method of International Publication No. WO 02/45143, a series of parallel channels or slots 2 is formed in the wafer 3. The slots are typically 0.05 mm wide, and the pitch of the slots is typically 0.1 mm. In this manner thin parallel strips of silicon 1 are formed, about 0.05 mm wide. Because the slots 2 do not extend all the way to the edges of wafer 3, a frame 5 of uncut silicon holds the strips 1 in place. Frame 5 is typically 5 mm wide on each side. Slots 2 may be formed using any of a number of techniques, including those referred to in International Publication No. WO 02/45143.
FIG. 1(b) is an enlarged vertical cross-section through the wafer 3 along line A-A showing strips 1 and spaces 2 in cross-sectional view.
FIG. 2 illustrates an arrangement of strips or slivers fabricated as solar cells 20 with a parallel connection and a gap between cells. The cells 20 are arranged on a substrate 21 as shown. Electrically conductive tracks 16 may be formed, for example, so that all the p polarity contacts 32 are electrically connected together at one end of the cells, while the n polarity contacts 33 are electrically connected together at the other end of the cells.
As the strips or slivers of semiconductor readily warp and bend but at the same time are quite brittle, the slivers disadvantageously may fracture or be damaged when separated from the wafer. Further, the faces of all slivers must all be configured with the same face as shown as cells 20 in FIG. 2, or differences in polarity may occur. Still further, the slivers may disadvantageously stick together.
Therefore, a need exists for separating strips or slivers of semiconductor material from wafers and assembling those separated strips or slivers.